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Transfer - Whenver You ___ It

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I/O Interface (Interrupt and DMA Mode)

The method that is used to transfer information betwixt internal storage and external I/O devices is known as I/O interface. The CPU is interfaced using special advice links past the peripherals continued to any figurer system. These communication links are used to resolve the differences betwixt CPU and peripheral. There exists special hardware components between CPU and peripherals to supervise and synchronize all the input and output transfers that are chosen interface units.

Manner of Transfer:

The binary information that is received from an external device is usually stored in the retentiveness unit of measurement. The information that is transferred from the CPU to the external device is originated from the memory unit. CPU only processes the information simply the source and target is e'er the memory unit. Data transfer betwixt CPU and the I/O devices may be done in different modes.

Information transfer to and from the peripherals may exist done in any of the 3 possible ways

  1. Programmed I/O.
  2. Interrupt- initiated I/O.
  3. Directly memory access( DMA).

Now let'south discuss each mode i by one.

  1. Programmed I/O: It is due to the result of the I/O instructions that are written in the computer program. Each information item transfer is initiated by an instruction in the programme. Unremarkably the transfer is from a CPU register and memory. In this case it requires constant monitoring by the CPU of the peripheral devices.

    Example of Programmed I/O: In this case, the I/O device does not have direct access to the memory unit. A transfer from I/O device to memory requires the execution of several instructions past the CPU, including an input didactics to transfer the data from device to the CPU and store instruction to transfer the data from CPU to memory. In programmed I/O, the CPU stays in the plan loop until the I/O unit indicates that it is ready for data transfer. This is a time consuming procedure since it needlessly keeps the CPU busy. This situation can be avoided past using an interrupt facility. This is discussed below.

  2. Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy unnecessarily. This situation can very well be avoided by using an interrupt driven method for data transfer. Past using interrupt facility and special commands to inform the interface to event an interrupt request signal whenever data is available from any device. In the meantime the CPU can go along for any other program execution. The interface meanwhile keeps monitoring the device. Whenever it is adamant that the device is set for information transfer it initiates an interrupt asking signal to the computer. Upon detection of an external interrupt point the CPU stops momentarily the task that it was already performing, branches to the service programme to process the I/O transfer, then return to the task it was originally performing.

    Annotation: Both the methods programmed I/O and Interrupt-driven I/O require the agile intervention of the
    processor to transfer information between memory and the I/O module, and any data transfer must transverse
    a path through the processor. Thus both these forms of I/O suffer from two inherent drawbacks.

    • The I/O transfer charge per unit is limited by the speed with which the processor can test and service a
      device.
    • The processor is tied upwards in managing an I/O transfer; a number of instructions must exist executed
      for each I/O transfer.
  3. Directly Memory Access: The data transfer between a fast storage media such as magnetic disk and memory unit is limited by the speed of the CPU. Thus nosotros can allow the peripherals direct communicate with each other using the retentivity buses, removing the intervention of the CPU. This blazon of information transfer technique is known as DMA or direct retentivity access. During DMA the CPU is idle and information technology has no control over the memory buses. The DMA controller takes over the buses to manage the transfer directly between the I/O devices and the memory unit.

    Bus Request : It is used by the DMA controller to request the CPU to relinquish the control of the buses.

    Bus Grant : It is activated past the CPU to Inform the external DMA controller that the buses are in high impedance state and the requesting DMA tin can take control of the buses. Once the DMA has taken the command of the buses it transfers the information. This transfer can take place in many ways.

    Types of DMA transfer using DMA controller:

    Burst Transfer :
    DMA returns the double-decker after consummate information transfer. A register is used as a byte count,
    being decremented for each byte transfer, and upon the byte count reaching zero, the DMAC will
    release the bus. When the DMAC operates in outburst way, the CPU is halted for the duration of the data
    transfer.
    Steps involved are:

    1. Motorbus grant request fourth dimension.
    2. Transfer the entire block of information at transfer rate of device because the device is usually wearisome than the
      speed at which the data tin can be transferred to CPU.
    3. Release the control of the autobus back to CPU
      So, total time taken to transfer the N bytes
      = Bus grant request time + (N) * (memory transfer rate) + Bus release command time.
    Where, X µsec =information transfer time or training time (words/block) Y µsec =memory wheel time or cycle time or transfer time (words/cake) % CPU idle (Blocked)=(Y/X+Y)*100 % CPU Busy=(X/X+Y)*100

    Cyclic Stealing :
    An alternative method in which DMA controller transfers ane word at a time after which it must return the command of the buses to the CPU. The CPU delays its operation only for one memory cycle to allow the straight memory I/O transfer to "steal" one memory bicycle.
    Steps Involved are:

    1. Buffer the byte into the buffer
    2. Inform the CPU that the device has 1 byte to transfer (i.e. passenger vehicle grant request)
    3. Transfer the byte (at arrangement bus speed)
    4. Release the control of the motorcoach back to CPU.

      Before moving on transfer next byte of information, device performs step i once more so that bus isn't tied up and
      the transfer won't depend upon the transfer charge per unit of device.
      So, for ane byte of transfer of data, fourth dimension taken by using cycle stealing mode (T).
      = time required for coach grant + 1 bus wheel to transfer data + fourth dimension required to release the bus, it will be
      North x T

    In wheel stealing mode nosotros ever follow pipelining concept that when one byte is getting transferred then Device is parallel preparing the next byte. "The fraction of CPU time to the data transfer time" if asked then cycle stealing mode is used.

    Where, X µsec =information transfer time or preparation time (words/block) Y µsec =retentivity bike time or cycle time or transfer fourth dimension (words/cake) % CPU idle (Blocked) =(Y/X)*100 % CPU busy=(X/Y)*100

    Interleaved style: In this technique , the DMA controller takes over the arrangement bus when the
    microprocessor is not using it.An alternating half bike i.e. half cycle DMA + half cycle processor.

    Note: In Gate Examination you can directly utilise above formula for dissimilar mode of DMA transfer.

    This article is contributed by Namita Singh.

    Delight write comments if yous discover annihilation incorrect, or you desire to share more information about the topic discussed in a higher place.

mccollumnothater.blogspot.com

Source: https://www.geeksforgeeks.org/io-interface-interrupt-dma-mode/

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